1. Field of Invention
The present invention relates to a logic circuit, and more particularly to a tree-style AND-type match circuit device applied to the content addressable memory.
2. Description of Related Art
The searching speed and power consumption of the content addressable memory (CAM) are affected by the match circuit. Match circuit designs are generally divided into NOR-type match circuit devices and NAND-type match circuit devices. NAND-type match circuit devices have lower power consumption but with slow searching speed; NOR-type match circuit devices have high searching speed but with high power consumption. Even though some methods like reducing the voltage swing and the direct current can improve the power consumption problem, these methods still cannot efficiently improve the power consumption problem of NOR-type match circuits.
Reference is made to FIG. 1, which illustrates a PF-CDPD (Pseudo-footless clock-and-data precharged dynamic) logic circuit in accordance with the prior art. The PF-CDPD logic circuit is used in the design of the match circuit 400 in the content addressable memory. In the scheme of the match circuit 400, a plurality of active AND logic gates 410 cascade in order. If one stage of these active AND logic gates 410 does not work, all the later logic gates do not act. This kind of circuit is similar to a NAND logic circuit so the power consumption is very low. Furthermore, all the gates G of the NMOS 411 are determined before the evaluation of the active AND logic gates 410 such that if the inputs of a single stage are all logic “1” (all the data of a single stage are matched successfully), the drain D and source S have zero potential, the same effect as grounding. Therefore, every stage of the PF-CDPD is like having only two inverters such that the searching speed is greatly enhanced. However, because the amount of the NMOS 411 stacked in each active AND logic gate 410 are limited by the charge sharing effect, the delay time of the match circuit 400 is still long because many cascaded stages are required for a match circuit.
Reference is made to FIG. 2, in order to solve the delay problem, one method is to draw out from the critical path of the match circuit with parallel-processing gates. Consequently, the evaluation speed of the new circuit path gets faster because the number of NMOS stacks is reduced. However, the method increases not only the loading of the clock signal but also the power consumption of content addressable memory.
Besides, the feature of the match circuit in FIG. 1 which determines the later stages act or not doesn't exist in the drawn out gates in FIG. 2, so the power consumption of the match circuit in FIG. 2 is larger than the power consumption of the match circuit in FIG. 1.
According to the aforementioned description, the match circuit 400 in FIG. 1 greatly reduces power consumption, but it suffers from the serious delay problem. On the other hand, the match circuit of FIG. 2 accelerates the evaluation speed, but it causes high power consumption problem. So, it is necessary to find an optimized solution to improve these two problems simultaneously.